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19-3826; Rev 1; 6/07
KIT ATION EVALU BLE AVAILA
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
Features
Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit, 45Msps Tx DAC Ultra-Low Power 84.6mW at fCLK = 45MHz, Fast Mode 77.1mW at fCLK = 45MHz, Slow Mode Low-Current Standby and Shutdown Modes Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim Excellent Dynamic Performance SNR = 54.2dB at fIN = 5.5MHz (Rx ADC) SFDR = 73.2dBc at fOUT = 2.2MHz (Tx DAC) Three 12-Bit, 1s Aux-DACs 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging Excellent Gain/Phase Match 0.03 Phase, 0.01dB Gain (Rx ADC) at fIN = 5.5MHz Multiplexed Parallel Digital I/O Serial-Interface Control Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable Miniature 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
General Description
The MAX19707 is an ultra-low-power, mixed-signal analog front-end (AFE) designed for power-sensitive communication equipment. Optimized for high dynamic performance at ultra-low power, the device integrates a dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit, 45Msps transmit (Tx) DAC; three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control; and a 10-bit, 333ksps housekeeping aux-ADC. The typical operating power in Tx-Rx FAST mode is 84.6mW at a 45MHz clock frequency. The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR at fIN = 5.5MHz and fCLK = 45MHz. The analog I/Q input amplifiers are fully differential and accept 1.024VP-P full-scale signals. Typical I/Q channel matching is 0.03 phase and 0.01dB gain. The Tx DACs feature 73.2dBc SFDR at fOUT = 2.2MHz and fCLK = 45MHz. The analog I/Q full-scale output voltage is 400mV differential. The Tx DAC common-mode DC level is programmable from 0.71V to 1.05V. The I/Q channel offset is programmable to optimize radio lineup sideband/carrier suppresion. The typical I/Q channel matching is 0.01dB gain and 0.07 phase. The Rx ADC and Tx DAC share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (TDD) applications. A 3-wire serial interface controls power-management modes, the aux-DAC channels, and the aux-ADC channels. The MAX19707 operates on a single 2.7V to 3.3V analog supply and 1.8V to 3.3V digital I/O supply. The MAX19707 is specified for the extended (-40C to +85C) temperature range and is available in a 48-pin, thin QFN package. The Selector Guide at the end of the data sheet lists other pin-compatible versions in this AFE family.
MAX19707
Pin Configuration
DAC3 ADC1 ADC2 VDD GND VDD SCLK DIN T/R TOP VIEW DOUT SHDN
24 23 22 21 20 19 18 17 16
36 35 34 33 32 31 30 29 28 27 26 25
CS
DAC2 DAC1 VDD IDN IDP GND VDD QDN QDP REFIN COM REFN
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
D9 D8 D7 D6 OVDD OGND D5 D4 D3 D2 D1 D0
Applications
WiMAX CPEs 802.11a/b/g WLAN VoIP Terminals Portable Communication Equipment
MAX19707
Ordering Information
PART* MAX19707ETM MAX19707ETM+ PIN-PACKAGE 48 Thin QFN-EP** 48 Thin QFN-EP** PKG CODE T4877-4 T4877-4
EXPOSED PADDLE (GND)
15 14 13
REFP VDD
IAP IAN GND CLK
GND VDD QAN QAP
*All devices are specified over the -40C to +85C operating range. **EP = Exposed paddle. +Denotes lead-free package.
THIN QFN
Functional Diagram and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
GND
VDD
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND-0.3V to (VDD + 0.3V)D0-D9, DOUT, T/R, SHDN, SCLK, DIN, CS, CLK to OGND .....................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derate 27.8mW/C above +70C) .....2.22W Thermal Resistance JA ..................................................36C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage VDD OVDD Ext1-Tx, Ext3-Tx, and SPI2-Tx states; transmit DAC operating mode (Tx): fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON Ext2-Tx, Ext4-Tx, and SPI4-Tx states; transmit DAC operating mode (Tx): fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON VDD Supply Current Ext1-Rx, Ext4-Rx, and SPI3-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON Ext2-Rx, Ext3-Rx, and SPI1-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 2.7 1.8 3.0 3.3 VDD V V SYMBOL CONDITIONS MIN TYP MAX UNITS
16.5
29.8
35
mA
28.2
34
25.7
2
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON VDD Supply Current Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON Shutdown mode: CLK = 0 or OVDD Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx, SPI1-Rx, SPI3-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx, SPI2-Tx, SPI4-Tx states; transmit DAC operating mode (Tx), fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON Shutdown mode: CLK = 0 or OVDD Rx ADC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DC Gain Matching Offset Matching Gain Temperature Coefficient Power-Supply Rejection PSRR Offset error (VDD 5%) Gain error (VDD 5%) N INL DNL Residual DC offset error Include reference error -5 -5.5 -0.15 10 1.6 0.7 0.5 1.0 0.01 13 30 0.4 0.1 +5 +5.5 +0.15 Bits LSB LSB %FS %FS dB LSB ppm/C LSB %FS MIN TYP 3.2 MAX 5 mA 12.1 1 15 A UNITS
MAX19707
7.7
mA
OVDD Supply Current
485
A
1 76 1
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3
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER Rx ADC ANALOG INPUT Input Differential Range Input Common-Mode Voltage Range Input Impedance Rx ADC CONVERSION RATE Maximum Clock Frequency Data Latency (Figure 3) Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Third-Harmonic Distortion Intermodulation Distortion Third-Order Intermodulation Distortion Total Harmonic Distortion Aperture Delay Overdrive Recovery Time Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Amplitude Matching Phase Matching fINX,Y = 5.5MHz at -0.5dBFS, fINX,Y = 1.8MHz at -0.5dBFS (Note 4) fIN = 5.5MHz at -0.5dBFS (Note 5) fIN = 5.5MHz at -0.5dBFS (Note 5) -90 0.01 0.03 dB dB Degrees 1.5x full-scale input SNR SINAD SFDR HD3 IMD IM3 THD fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz 62.1 52.2 52.5 54.2 54.1 54.1 54 71.2 70.4 -78.1 -73.1 -68.6 -79.2 -68.4 -68.8 3.5 2 -61.5 dB dB dBc dBc dBc dBc dBc ns ns fCLK (Note 2) Channel I Channel Q 5 5.5 45 MHz Clock Cycles VID VCM RIN CIN Switched capacitor load Differential or single-ended inputs 0.512 VDD / 2 120 5 V V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS
4
_______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER Tx DAC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Residual DC Offset Full-Scale Gain Error Tx DAC DYNAMIC PERFORMANCE DAC Conversion Rate In-Band Noise Density Third-Order Intermodulation Distortion Glitch Impulse Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist Signal-to-Noise Ratio to Nyquist I-to-Q Output Isolation Gain Mismatch Between DAC Outputs Phase Mismatch Between DAC Outputs Differential Output Impedance Tx DAC ANALOG OUTPUT Full-Scale Output Voltage VFS Bits CM1 = 0, CM0 = 0 (default) Output Common-Mode Voltage VCOM Bits CM1 = 0, CM0 = 1 Bits CM1 = 1, CM0 = 0 Bits CM1 = 1, CM0 = 1 1.0 400 1.05 0.95 0.80 0.71 1.1 V mV SFDR THD SNR fCLK = 45MHz, fOUT = 2.2MHz fCLK = 45MHz, fOUT = 2.2MHz fCLK = 45MHz, fOUT = 2.2MHz fOUTX,Y = 2MHz, fOUTX,Y = 2.2MHz Measured at DC TA +25C TA < +25C -0.3 -0.42 0.07 800 60 fCLK ND IM3 (Note 2) fOUT = 2.2MHz, fCLK = 45MHz f1 = 2MHz, f2 = 2.2MHz -130.6 80 10 73.2 -71 57.1 85 0.01 +0.3 +0.42 -59 45 MHz dBc/Hz dBc pV*s dBc dB dB dB dB Degrees N INL DNL VOS Guaranteed monotonic (Note 6) TA +25C TA < +25C Include reference error (peak-to-peak error) TA +25C TA < +25C -1 -4 -4.5 -30 -40 10 0.3 0.2 1 1 +1 +4 +4.5 +30 +40 Bits LSB LSB mV mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19707
Tx DAC INTERCHANNEL CHARACTERISTICS
fOUT = 2.2MHz, fCLK = 45MHz
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5
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS ADC fINI = fINQ = 5.5MHz, DAC fOUTI = fOUTQ = 2.2MHz, fCLK = 45MHz N VREF AD1 = 0 (default) AD1 = 1 MIN TYP MAX UNITS
Rx ADC-Tx DAC INTERCHANNEL CHARACTERISTICS Receive Transmit Isolation AUXILIARY ADC (ADC1, ADC2) Resolution Full-Scale Reference Analog Input Range Analog Input Impedance Input-Leakage Current Gain Error Zero-Code Error Differential Nonlinearity Integral Nonlinearity Supply Current AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Zero-Code Error Output-Voltage Low Output-Voltage High DC Output Impedance Settling Time Glitch Impulse Rx ADC-Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid CLK Fall to Channel-Q Output Data Valid I-DAC DATA to CLK Fall Setup Time tDOI tDOQ tDSI Figure 3 (Note 6) Figure 3 (Note 6) Figure 5 (Note 6) 5.4 7.3 9 6.5 8.8 8.1 11.1 ns ns ns N INL DNL GE ZE VOL VOH RL > 200k RL > 200k DC output at midscale From 1/4 FS to 3/4 FS, within 10 LSB From 0 to FS transition 2.56 4 1 24 Guaranteed monotonic over codes 100 to 4000 (Note 6) RL > 200k -1.0 (Note 6) 12 1.25 0.65 0.7 0.6 0.1 +1.1 Bits LSB LSB %FS %FS V V s nV*s GE ZE DNL INL At DC Measured at unselected input from 0 to VREF Includes reference error -5 2 0.53 0.45 210 85 dB
10 2.048 VDD 0 to VREF 500 0.1 +5
Bits V V k A %FS mV LSB LSB A
6
_______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER Q-DAC DATA to CLK Rise Setup Time CLK Fall to I-DAC Data Hold Time CLK Rise to Q-DAC Data Hold Time CLK Duty Cycle CLK Duty-Cycle Variation Digital Output Rise/Fall Time Falling Edge of CS to Rising Edge of First SCLK Time DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Period SCLK to CS Setup Time CS High Pulse Width CS High to DOUT Active High CS High to DOUT Low (Aux-ADC Conversion Time) DOUT Low to CS Setup Time SCLK Low to DOUT Data Out CS High to DOUT High Impedance 20% to 80% SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6) tCSS tDS tDH tCH tCL tCP tCS tCSW tCSD tCONV tDCS tCD tCHZ Bit AD0 set Bit AD0 set, no averaging (see Table 14), fCLK = 45MHz, CLK divider = 16 (see Table 15) Bit AD0, AD10 set Bit AD0, AD10 set Bit AD0, AD10 set From shutdown to Rx mode, ADC settles to within 1dB SINAD Shutdown Wake-Up Time tWAKE,SD From shutdown to Tx mode, DAC settles to within 10 LSB error From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD Idle Wake-Up Time (With CLK) tWAKE,ST0 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error From standby to Rx mode, ADC settles to within 1dB SINAD Standby Wake-Up Time tWAKE,ST1 From standby to Tx mode, DAC settles to 10 LSB error 200 10 10 0 25 25 50 10 80 200 4.27 200 14.5 ns ns ns ns ns ns ns ns ns s ns ns ns SYMBOL tDSQ tDHI tDHQ CONDITIONS Figure 5 (Note 6) Figure 5 (Note 6) Figure 5 (Note 6) MIN 9 -4 -4 50 15 2.6 TYP MAX UNITS ns ns ns % % ns
MAX19707
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) 85.2 s 28.2 9.8 s 6.4 13.7 s 24
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7
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER Enable Time from Tx to Rx, (Ext2Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx, and SPI4-Tx to SPI3-Rx States) Enable Time from Rx to Tx, (Ext1Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx, and SPI3-Rx to SPI4-Tx States) Enable Time from Tx to Rx, (Ext1Tx to Ext1-Rx, Ext3-Tx to Ext3-Rx, and SPI1-Tx to SPI2-Rx States) Enable Time from Rx to Tx, (Ext2Rx to Ext2-Tx, Ext3-Rx to Ext3-Tx, and SPI1-Rx to SPI2-Tx States) SYMBOL CONDITIONS MIN TYP 500 MAX UNITS ns
tENABLE, RX ADC settles to within 1dB SINAD
tENABLE, TX DAC settles to within 10 LSB error
500
ns
tENABLE, RX ADC settles to within 1dB SINAD
4.1
s
tENABLE, TX DAC settles to within 10 LSB error
7.0
s
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) Positive Reference Negative Reference Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current Differential Reference Output Differential Reference Temperature Coefficient Reference Input Voltage Differential Reference Output Common-Mode Output Voltage Maximum REFP/REFN/COM Source Current Maximum REFP/REFN/COM Sink Current REFIN Input Current REFIN Input Resistance VCOM ISOURCE ISINK VREF REFTC VREFP - VREFN +0.489 VREFP - VCOM VREFN - VCOM 0.256 -0.256 VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 2 2 +0.512 10 +0.534 V V V mA mA V ppm/C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) VREFIN VDIFF VCOM ISOURCE ISINK VREFP - VREFN 1.024 0.512 VDD / 2 2 2 -0.7 500 V V V mA mA A k
8
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input High Threshold Input Low Threshold Input Leakage Input Capacitance DIGITAL OUTPUTS (D0-D9, DOUT) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance VOL VOH ILEAK COUT ISINK = 200A ISOURCE = 200A 0.8 x OVDD -1 5 +1 0.2 x OVDD V V A pF SYMBOL VINH VINL DIIN DCIN D0-D9, CLK, SCLK, DIN, CS, T/R, SHDN = OGND or OVDD -1 5 CONDITIONS MIN TYP MAX UNITS V 0.3 x OVDD +1 V A pF DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0-D9, T/R, SHDN) 0.7 x OVDD
Note 1: Specifications from TA = +25C to +85C are guaranteed by production tests. Specifications from TA = +25C to -40C are guaranteed by design and characterization. Note 2: The minimum clock frequency (fCLK) for the MAX19707 is 7.5MHz (typical). The minimum aux-ADC sample rate clock frequency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 7.5MHz / 128 = 58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPITM. The maximum conversion time (for no averaging, NAVG = 1) will be, tCONV (max) = (12 x 1 x 128) / 7.5MHz = 205s. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone. Note 5: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization. SPI is a trademark of Motorola, Inc.
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9
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Typical Operating Characteristics
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC CHANNEL-IA FFT PLOT
MAX19707 toc01
Rx ADC CHANNEL-QA FFT PLOT
MAX19707 toc02
Rx ADC CHANNEL-IA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 fCLK = 45.006848MHz f1 = 1.4MHz f2 = 1.8MHz AIA = -7dBFS PER TONE 8192-POINT DATA RECORD
MAX19707 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0
fCLK = 45.006848MHz fIA = 13.00155MHz 16,384-POINT DATA RECORD
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100
fCLK = 45.006848MHz fQA = 13.00155MHz 16,384-POINT DATA RECORD
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
Rx ADC CHANNEL-QA TWO-TONE FFT PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz) 50 0 fCLK = 45.006848MHz f1 = 1.4MHz f2 = 1.8MHz AQA = -7dBFS PER TONE 8192-POINT DATA RECORD
MAX19707 toc04
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX19707 toc05
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY
MAX19707 toc06
0
56 55 54 SNR (dB) 53 52 IA 51 QA
56 55 54 SINAD (dB) 53 52 IA 51 50 QA
20
40
60
80
100
0
20
40
60
80
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX19707 toc07
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
MAX19707 toc08
Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE
fIN = 13.00155MHz QA
MAX19707 toc09
-55 -60 -65 QA
85
60 50 40 SNR (dB)
80 QA
SFDR (dBc)
THD (dBc)
-70 -75 -80 -85 IA
75
IA 30 20
70 IA
65 -90 -95 0 20 40 60 80 100 ANALOG INPUT FREQUENCY (MHz) 60 0 20 40
10 0 60 80 100 -21 -18 -15 -12 -9 -6 -3 0 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT AMPLITUDE (dBFS)
10
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE
MAX19707 toc10
MAX19707
Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT AMPLITUDE
MAX19707 toc11
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE
fIN = 12.4980346MHz
MAX19707 toc12
60 50 40 SINAD (dB)
fIN = 13.00155MHz
-40 -45 -50
QA
fIN = 12.4980346MHz
75 70 65
IA 30 20 10 0 -21 -18 -15 -12 -9 -6 -3 0 ANALOG INPUT AMPLITUDE (dBFS)
-60 -65 -70 -75 -80 -21 -18 -15 -12 -9 -6
QA
SFDR (dBc)
THD (dBc)
-55
QA
60 55 50 IA
IA 45 -3 0 -21 -18 -15 -12 -9 -6 -3 0 ANALOG INPUT AMPLITUDE (dBFS) ANALOG INPUT AMPLITUDE (dBFS)
Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX19707 toc13
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE
fIN = 12.4980346MHz
MAX19707 toc14
Rx ADC TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
fIN = 12.4980346MHz QA -60 -65
MAX19707 toc15
56
57
-55
fIN = 12.4980346MHz IA
56 IA SINAD (dB)
55 SNR (dB)
THD (dBc)
55
-70 -75 -80 IA
54 QA 53
54 QA 53
-85 -90
52 5 10 15 20 25 30 35 40 45 SAMPLING RATE (MHz)
52 5 10 15 20 25 30 35 40 45 SAMPLING RATE (MHz)
-95 5 10 15 20 25 30 35 40 45 SAMPLING RATE (MHz)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX19707 toc16
Rx ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX19707 toc17
Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE
fIN = 12.4980346MHz
MAX19707 toc18
90 85 80 SFDR (dBc) 75 70 65 60 5
fIN = 12.4980346MHz
57
fIN = 12.4980346MHz
57
56 QA
56 QA
IA SINAD (dB) SNR (dB) 55 55
54 IA 53
54 IA
QA
53
52 10 15 20 25 30 35 40 45 35 45 55 65 SAMPLING RATE (MHz) CLOCK DUTY CYCLE (%)
52 35 45 55 65 CLOCK DUTY CYCLE (%)
______________________________________________________________________________________
11
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
MAX19707 toc19
Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
MAX19707 toc20
Rx ADC OFFSET ERROR vs. TEMPERATURE
0.8 0.6 OFFSET ERROR (%FS) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 QA IA
MAX19707 toc21
-55 -60 -65 THD (dBc) -70 -75 -80 -85 -90 -95 35
fIN = 12.4980346MHz QA
90 85
1.0
fIN = 12.4980346MHz
IA 80 SFDR (dBc) 75 70 QA 65 60
IA
-1.0 35 45 55 65 -40 -15 10 35 60 85 CLOCK DUTY CYCLE (%) TEMPERATURE (C)
45
55
65
CLOCK DUTY CYCLE (%)
Rx ADC GAIN ERROR vs. TEMPERATURE
MAX19707 toc22
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
MAX19707 toc23
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY
MAX19707 toc24
2.0 1.8 1.6 GAIN ERROR (%FS) 1.4 QA
74 fOUT = fCLK / 10 73 72 SFDR (dBc) 71 70 69 68 67 66
75 70 65 SFDR (dBc) 60 55 50 45
1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -15 10 35 60 85 TEMPERATURE (C) IA
5
10
15
20
25
30
35
40
45
0
2
4
6
8 10 12 14 16 18 20 22
SAMPLING RATE (MHz)
OUTPUT FREQUENCY (MHz)
Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE
MAX19707 toc25
Tx DAC CHANNEL-ID SPECTRAL PLOT
MAX19707 toc26
Tx DAC CHANNEL-QD SPECTRAL PLOT
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 fQD = 5.498MHz
MAX19707 toc27
80 75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 -30 -20 -10 0 OUTPUT AMPLITUDE (dBFS) fOUT = 2.2MHz
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 0
fID = 5.498MHz
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz)
12
______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
Rx ADC INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX19707 toc28 MAX19707 toc29
SUPPLY CURRENT vs. SAMPLING RATE
30 Ext4-Rx MODE 28 SUPPLY CURRENT (mA) 26 24 22 20 18 16 5 10 15 20 25 30 35 40 45 SAMPLING RATE (MHz) IVDD INL (LSB) 1.0 0.8 0.6 0.4
Rx ADC DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX19707 toc30
0.5
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
Tx DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX19707 toc31
Tx DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX19707 toc32
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
VREFP - VREFN
MAX19707 toc33
1.0 0.8 0.6 0.4
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
0.520
0.515 VREFP - VREFN (V)
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE
0.510
0.505
0.500 0 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE -40 -15 10 35 60 85 TEMPERATURE (C)
AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX19707 toc34
AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
MAX19707 toc35
AUX-DAC SETTLING TIME
STEP FROM 1/4FS TO 3/4FS
MAX19707 toc36
3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0.001
3.0 2.5 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0.001
500mV/div
0.01
0.1
1
10
100
0.01
0.1
1
10
100
500ns/div
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
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13
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33F, TA = +25C, unless otherwise noted.)
AUX-DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX19707 toc37
AUX-DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 0 1024 2048 3072 4096
MAX19707 toc38
2.0 1.5 1.0 0.5 INL (LSB) 0 -0.5 -1.0 -1.5 -2.0 0 1024 2048 3072
0.8
4096
DIGITAL INPUT CODE
DIGITAL INPUT CODE
AUX-ADC INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX19707 toc39
AUX-ADC DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX19707 toc40
2.0 1.5 1.0 INL (LSB)
0.8
0.4 DNL (LSB) 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
0.5 0 -0.5 -1.0 -1.5 -2.0
0
-0.4
-0.8 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE
Pin Description
PIN 1 2, 8, 11, 31, 33, 39, 43 3 4 5, 7, 12, 32, 42 6 9 NAME REFP VDD IAP IAN GND CLK QAN FUNCTION Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible. Analog Supply Voltage. Supply range from 2.7V to 3.3V. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP. Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM. Analog Ground. Connect all GND pins to ground plane. Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
14
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
Pin Description (continued)
PIN 10 13-18, 21-24 19 20 25 26 27 28 29 30 34 35 36 37 38 40, 41 44, 45 46 47 48 -- NAME QAP D0-D9 OGND OVDD SHDN DOUT T/R DIN SCLK CS ADC2 ADC1 DAC3 DAC2 DAC1 IDN, IDP QDN, QDP REFIN COM REFN EP FUNCTION Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP. Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). Output-Driver Ground Output-Driver Power Supply. Supply range from 1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2F capacitor in parallel with a 0.1F capacitor. Active-Low Shutdown Input. Apply logic-low to place the MAX19707 in shutdown. Aux-ADC Digital Output Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A logic-high input sets the device in transmit mode. 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface. Analog Input for Auxiliary ADC Analog Input for Auxiliary ADC Analog Output for Auxiliary DAC3 Analog Output for Auxiliary DAC2 Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up) DAC Channel-ID Differential Voltage Output DAC Channel-QD Differential Voltage Output Reference Input. Connect to VDD for internal reference. Bypass to GND with a 0.1F capacitor. Common-Mode Voltage I/O. Bypass COM to GND with a 0.33F capacitor. Negative Reference I/O. Rx ADC conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.33F capacitor. Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
MAX19707
Detailed Description
The MAX19707 integrates a dual, 10-bit Rx ADC and a dual, 10-bit Tx DAC while providing ultra-low power and high dynamic performance at a 45Msps conversion rate. The Rx ADC analog input amplifiers are fully differential and accept 1.024VP-P full-scale signals. The Tx DAC analog outputs are fully differential with 400mV full-scale output, selectable common-mode DC level, and adjustable I/Q offset trim. The MAX19707 integrates three 12-bit auxiliary DAC (aux-DAC) channels and a 10-bit, 333ksps auxiliary ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC channels feature 1s settling time for fast automatic gain-control (AGC), variable-gain amplifier (VGA), and
automatic frequency-control (AFC) level setting. The aux-ADC features data averaging to reduce processor overhead and a selectable clock-divider to program the conversion rate. The MAX19707 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI and MICROWIRETM compatible. The MAX19707 serial interface selects shutdown, idle, standby, transmit (Tx), and receive (Rx) modes, as well as controls aux-DAC and aux-ADC channels. The Rx ADC and Tx DAC share a common digital I/O to reduce the digital interface to a single, 10-bit parallel multiplexed bus. The 10-bit digital bus operates on a single 1.8V to 3.3V supply.
MICROWIRE is a trademark of National Semiconductor Corp.
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15
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Dual, 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is VREF with a VDD / 2 0.2V common-mode input range. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP and IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the Rx ADC range of VDD / 2 (200mV) for optimum performance.
INTERNAL BIAS S2a C1a S4a IAP C2a S4c S1
COM S5a S3a
OUT
IAN S4b C2b C1b S3b S2b INTERNAL BIAS INTERNAL BIAS S2a C1a S4a QAP C2a S4c S1 S5b COM
OUT
HOLD TRACK
HOLD TRACK
CLK INTERNAL NONOVERLAPPING CLOCK SIGNALS
COM S5a S3a
OUT
MAX19707
OUT
QAN S4b C2b C1b S3b S2b INTERNAL BIAS S5b COM
Figure 1. Rx ADC Internal T/H Circuits
16
______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT VOLTAGE VREF x 512/512 VREF x 511/512 VREF x 1/512 VREF x 0/512 -VREF x 1/512 -VREF x 511/512 -VREF x 512/512 DIFFERENTIAL INPUT (LSB) 511 (+Full Scale - 1 LSB) 510 (+Full Scale - 2 LSB) +1 0 (Bipolar Zero) -1 -511 (-Full Scale +1 LSB) -512 (-Full Scale) OFFSET BINARY (D0-D9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 OUTPUT DECIMAL CODE 1023 1022 513 512 511 1 0
1 LSB =
2 x VREF 1024 VREF
VREF = VREFP - VREFN VREF
OFFSET BINARY OUTPUT CODE (LSB)
10 0000 0001 10 0000 0000 01 1111 1111
00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000
-512 -511 -510 -509
-1 0+ 1 (COM) INPUT VOLTAGE (LSB)
+509 +510 +511 +512
Figure 2. Rx ADC Transfer Function
Rx ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channel I (CHI) and channel Q (CHQ) are sampled on the rising edge of the clock signal (CLK) and the resulting data is
______________________________________________________________________________________
VREF
VREF
11 1111 1111 11 1111 1110 11 1111 1101
multiplexed at the D0-D9 outputs. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHI and 5.5 clock cycles for CHQ. Digital Input/Output Data (D0-D9) D0-D9 are the Rx ADC digital logic outputs when the MAX19707 is in receive mode. This bus is shared with the Tx DAC digital logic inputs and operates in halfduplex mode. D0-D9 are the Tx DAC digital logic inputs when the MAX19707 is in transmit mode. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs D0-D9 as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX19707 and degrading its dynamic performance. Buffers on the digital outputs isolate the outputs from heavy capacitive loads. Adding 100 resistors in series with the digital outputs close to the MAX19707 helps improve Rx ADC and Tx DAC performance. Refer to the MAX19707EVKIT schematic for an example of the digital outputs driving a digital buffer through 100 series resistors. During SHDN, IDLE, and STBY states, D0-D9 are internally pulled up to prevent floating digital inputs. To ensure no current flows through D0-D9 I/O, the external bus needs to be either tri-stated or pulled up to OVDD and should not be pulled to ground.
(COM)
17
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI)
CHI
CHQ tCL CLK
tCLK tCH
tDOQ D0-D9 D0Q D1I
tDOI D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q
Figure 3. Rx ADC System Timing Diagram
Dual, 10-Bit Tx DAC
The dual, 10-bit digital-to-analog converter (Tx DAC) operates with clock speeds up to 45MHz. The Tx DAC digital inputs, D0-D9, are multiplexed on a single 10-bit bus. The voltage reference determines the Tx DAC fullscale output voltage. See the Reference Configurations section for details on setting the reference voltage. The Tx DAC outputs at IDN, IDP and QDN, QDP are biased at a 0.7V to 1.05V adjustable DC commonmode bias and designed to drive a differential input stage with 70k input impedance. This simplifies the
analog interface between RF quadrature upconverters and the MAX19707. Many RF upconverters require a 0.7V to 1.05V common-mode bias. The Tx DAC DC common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode DC level. Table 2 shows the Tx DAC output voltage vs. input codes. Table 10 shows the selection of DC common-mode levels. See Figure 4 for an illustration of the Tx DAC analog output levels.
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = 400 for 800mVP-P Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (D0-D9) 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 INPUT DECIMAL CODE 1023 1022 513 512 511 1 0
(VFS ) VREFDAC x 1023 1024 1023 (VFS ) VREFDAC 1024 (VFS ) VREFDAC 1024 (VFS ) VREFDAC 1024 (VFS ) -VREFDAC 1024 (VFS ) -VREFDAC 1024
x x x 1021 1023 3 1023 1 1023 1 1023
x x
1021 1023 (VFS ) -VREFDAC x 1023 1024 1023
18
______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
The Tx DAC also features independent DC offset correction of each I/Q channel. This feature is configured through the SPI interface. The DC offset correction is used to optimize sideband and carrier suppression in the Tx signal path (see Table 9).
MAX19707
MAX19707
EXAMPLE: Tx DAC I-CH 0 90 Tx DAC Q-CH Tx RFIC INPUT REQUIREMENTS * DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (MAX) * BASEBAND INPUT = 400mV DC-COUPLED
FULL SCALE = 1.25V
VCOM = 1.05V
COMMON-MODE LEVEL
SELECT CM1 = 0, CM0 = 0 VCOM = 1.05V VDIFF = 400mV ZERO SCALE = 0.85V 0V
Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs
______________________________________________________________________________________
19
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I channel (ID) is latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal. composed of A3-A0 control bits and D11-D0 data bits. Data is shifted in MSB first (D11) and LSB last (A0). Tables 4, 5, and 6 show the MAX19707 operating modes and SPI commands. The serial interface remains active in all modes. SPI Register Description Program the control bits, A3-A0, in the register as shown in Table 3 to select the operating mode. Modify A3-A0 bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-DAC3, IOFFSET, QOFFSET, Aux-ADC, ENABLE-8, and COMSEL modes. ENABLE-16 is the default operating mode. This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx, and Tx modes. Table 4 shows the MAX19707 power-management modes. Table 5 shows the T/R pincontrolled external Tx-Rx switching modes. Table 6 shows the SPI-controlled Tx-Rx switching modes.
3-Wire Serial Interface and Operation Modes
The 3-wire serial interface controls the MAX19707 operation modes as well as the three 12-bit aux-DACs and the 10-bit aux-ADC. Upon power-up, program the MAX19707 to operate in the desired mode. Use the 3wire serial interface to program the device for shutdown, idle, standby, Rx, Tx, aux-DAC controls, or aux-ADC conversion. A 16-bit data register sets the mode control as shown in Table 3. The 16-bit word is
CLK tDSQ D0-D9 Q: N - 2 I: N - 1 tDSI tDHQ Q: N - 1 I: N tDHI Q: N I: N + 1
ID
N-2
N-1
N
QD
N-2
N-1
N
Figure 5. Tx DAC System Timing Diagram
20
______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 3. MAX19707 Mode Control
REGISTER NAME ENABLE-16 Aux-DAC1 Aux-DAC2 Aux-DAC3 IOFFSET QOFFSET COMSEL Aux-ADC ENABLE-8 D11 (MSB) E11 = 0 Reserved 1D11 2D11 3D11 -- -- -- AD11 = 0 Reserved -- D10 15 E10 = 0 Reserved 1D10 2D10 3D10 -- -- -- AD10 -- D9 14 E9 1D9 2D9 3D9 -- -- -- AD9 -- D8 13 -- 1D8 2D8 3D8 -- -- -- AD8 -- D7 12 -- 1D7 2D7 3D7 -- -- -- AD7 -- D6 11 E6 1D6 2D6 3D6 -- -- -- AD6 -- D5 10 E5 1D5 2D5 3D5 IO5 -- AD5 -- D4 9 E4 1D4 2D4 3D4 IO4 -- AD4 -- D3 8 E3 1D3 2D3 3D3 IO3 -- AD3 E3 D2 7 E2 1D2 2D2 3D2 IO2 -- AD2 E2 D1 6 E1 1D1 2D1 3D1 IO1 D0 5 E0 1D0 2D0 3D0 IO0 A3 4 0 0 0 0 0 0 0 0 1 A2 3 0 0 0 0 1 1 1 1 0 A1 2 0 0 1 1 0 0 1 1 0 A0 1 (LSB) 0 1 0 1 0 1 0 1 0
QO5 QO4 QO3 QO2 QO1 QO0 CM1 CM0 AD1 E1 AD0 E0
-- = Not used.
Table 4. Power-Management Modes
ADDRESS A3 A2 A1 A0 E9* DATA BITS E3 E2 E1 E0 T/R MODE PIN 27 FUNCTION (POWER MANAGEMENT) DESCRIPTION COMMENT
1X000
X
SHDN
SHUTDOWN
0000 (16-Bit Mode) or 1000 (8-Bit Mode)
XX001
X
IDLE
IDLE
Rx ADC = OFF Tx DAC = OFF Aux-DAC = OFF Aux-ADC = OFF CLK = OFF REF = OFF Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = ON REF = ON Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State Aux-ADC = OFF CLK = OFF REF = ON
Device is in complete shutdown. Overrides T/R pin.
Fast turn-on time. Moderate idle power. Overrides T/R pin.
1X010
X
STBY
STANDBY
Slow turn-on time. Low standby power. Overrides T/R pin.
X = Don't care. *Bit E9 is not available in 8-bit mode.
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21
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode)
ADDRESS DATA BITS T/R PIN 27 STATE FUNCTION Rx TO Tx-Tx TO Rx SWITCHING SPEED DESCRIPTION COMMENT
A3 A2 A1 A0 E3 E2 E1 E0
0 0011 1
Ext1-Rx FAST-SLOW Ext1-Tx
Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable SLOW-FAST Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enable Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable SLOW-SLOW Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable FAST-FAST Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enable
Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1.
Low Power: Slow Tx to Rx when T/R transitions 1 to 0.
0 0100 1
Ext2-Rx (Default)
Low Power: Slow Rx to Tx when T/R transitions 0 to 1.
0000 (16-Bit Mode) or 1000 (8-Bit Mode)
Ext2-Tx
Moderate Power: Fast Tx to Rx when T/R transitions 1 to 0.
0 0101 1
Ext3-Rx
Low Power: Slow Rx to Tx when T/R transitions 0 to 1.
Ext3-Tx
Low Power: Slow Tx to Rx when T/R transitions 1 to 0.
0 0110 1
Ext4-Rx
Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1.
Ext4-Tx
Moderate Power: Fast Tx to Rx when T/R transitions 1 to 0.
22
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 6. Tx-Rx Control Using SPI Commands
ADDRESS DATA BITS T/R PIN 27 MODE FUNCTION (Tx-Rx SWITCHING SPEED) DESCRIPTION COMMENTS
A3 A2 A1 A0 E3 E2 E1 E0
1011
X
SPI1-Rx
SLOW
Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enabled Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enabled
Low Power: Slow Rx to Tx through SPI command.
0000 (16-Bit Mode) or 1000 (8-Bit Mode)
1100
X
SPI2-Tx
SLOW
Low Power: Slow Tx to Rx through SPI command.
1101
X
SPI3-Rx
FAST
Moderate Power: Fast Rx to Tx through SPI command.
1110
X
SPI4-Tx
FAST
Moderate Power: Fast Tx to Rx through SPI command.
X = Don't care.
In ENABLE-16 mode, the aux-DACs have independent control bits E4, E5, and E6, and bit E9 enables the auxADC. Table 7 shows the auxiliary DAC enable codes and Table 8 shows the auxiliary ADC enable codes. Bits E11 and E10 are reserved. Program bits E11 and E10 to logic-low. Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11-_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19707 also includes two 6-bit registers that can be programmed to adjust the offsets for the Tx DAC I and Q channels independently (see Table 9). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 10). Use Aux-ADC mode to start the auxiliary ADC conversion (see the 10-Bit, 333ksps Auxiliary ADC section for details). Use ENABLE-8 mode for faster enable and switching between shutdown, idle, and standby states as well as switching between FAST, SLOW, and Rx and Tx modes.
Table 7. Aux-DAC Enable Table (ENABLE-16 Mode)
E6 0 0 0 0 1 1 1 1 E5 0 0 1 1 0 0 1 1 E4 0 1 0 1 0 1 0 1 AUX-DAC3 ON ON ON ON OFF OFF OFF OFF AUX-DAC2 ON ON OFF OFF ON ON OFF OFF AUX-DAC1 ON OFF ON OFF ON OFF ON OFF
Table 8. Aux-ADC Enable Table (ENABLE-16 Mode)
E9 0 (Default) 1 SELECTION Aux-ADC is Powered ON Aux-ADC is Powered OFF
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23
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 9. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode)
BITS IO5-IO0 WHEN IN IOFFSET MODE, BITS QO5-QO0 WHEN IN QOFFSET MODE IO5/QO5 1 1 1
* * *
IO4/QO4 1 1 1
* * *
IO3/QO3 1 1 1
* * *
IO2/QO2 1 1 1
* * *
IO1/QO1 1 1 0
* * *
IO0/QO0 1 0 1
* * *
OFFSET 1 LSB = (VFSP-P / 1023) -31 LSB -30 LSB -29 LSB
* * *
1 1 1 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
0 0 0 0 0 0
* * *
1 0 0 0 0 1
* * *
0 1 0 0 1 0
* * *
-2 LSB -1 LSB 0mV 0mV (Default) 1 LSB 2 LSB
* * *
0 0 0
1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
29 LSB 30 LSB 31 LSB
Note: For transmit full-scale of 400mV: 1 LSB = (800mVP-P / 1023) = 0.7820mV.
Table 10. Common-Mode Select (COMSEL Mode)
CM1 0 0 1 1 CM0 0 1 0 1 Tx DAC OUTPUT COMMON MODE (V) 1.05 (Default) 0.95 0.80 0.70
Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX19707 and placing the Rx ADC digital outputs in tri-state mode. When the Rx ADC outputs transition from tri-state to ON, the last converted word is placed on the digital outputs. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 85.2s to enter Rx mode and 28.2s to enter Tx mode. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The
24
Rx ADC outputs are forced to tri-state. The wake-up time is 9.8s to enter Rx mode and 6.4s to enter Tx mode. When the Rx ADC outputs transition from tristate to ON, the last converted word is placed on the digital outputs. In standby mode, the reference is powered, but the rest of the device functions are off. The wake-up time from standby mode is 13.7s to enter Rx mode and 24s to enter Tx mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. FAST and SLOW Rx and Tx Modes In addition to the external Tx-Rx control, the MAX19707 also features SLOW and FAST modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC core digital outputs are tri-stated on the D0-D9 bus; likewise, in FAST Rx mode, the transmit DAC core is powered on but the DAC core digital inputs are tri-stated on the D0-D9 bus. The switching time between Tx to Rx or Rx to Tx is FAST because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time between Rx to Tx and Tx to Rx is 0.5s.
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
However, power consumption is higher in this mode because both the Tx and Rx cores are always on. To prevent bus contention in these states, the Rx ADC output buffers are tri-stated during Tx and the Tx DAC input bus is tri-stated during Rx. In SLOW mode, the Rx ADC core is off during Tx; likewise the Tx DAC and filters are turned off during Rx to yield lower power consumption in these modes. For example, the power in SLOW Tx mode is 49.5mW. The power consumption during Rx is 77.1mW compared to 84.6mW power consumption in FAST mode. However, the recovery time between states is increased. The switching time in SLOW mode between Rx to Tx is 7s and Tx to Rx is 4.1s. R External T/R Switching Control vs. Serial-Interface Control Bit E3 in the ENABLE-16 or ENABLE-8 register determines whether the device Tx-Rx mode is controlled externally through the T/R input (E3 = low) or through the SPI command (E3 = high). By default, the MAX19707 is in the external Tx-Rx control mode. In the external control
MAX19707
mode, use the T/R input (pin 27) to switch between Rx and Tx modes. Using the T/R pin provides faster switching between Rx and Tx modes. To override the external Tx-Rx control, program the MAX19707 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface. SPI Timing The serial digital interface is a standard 3-wire connection compatible with SPI/QSPITM/MICROWIRE/DSP interfaces. Set CS low to enable the serial data loading at DIN or output at DOUT. Following a CS high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch when CS transitions high. CS must transition high for a minimum of 80ns before the next write sequence. The SCLK can idle either high or low between transitions. Figure 6 shows the detailed timing diagram of the 3-wire serial interface.
QSPI is a trademark of Motorola, Inc.
16-BIT OR 8-BIT WRITE INTO SPI (DIN)
16-BIT OR 8-BIT WRITE INTO SPI DURING AUX-ADC CONVERSION
10-BIT READ OUT OF AUX-ADC (DOUT) WITH SIMULTANEOUS 16-BIT WRITE INTO SPI (DIN)
tCSS CS tCSW
tCP
tCS
tCL tCH tDS SCLK tCSD
tCONV tDCS tCHZ
tCD tDH DIN MSB D11 (16-BIT) D3 (8-BIT) D10 (16-BIT) D2 (8-BIT) LSB A0 MSB LSB MSB BIT D11 (DIN) BIT D10 (DIN) BIT D1 (DIN) LSB BIT A0 (DIN)
DOUT
DOUT = TRI-STATED WHEN AUX-ADC IS IDLE
DOUT = ACTIVE WHEN BIT AD0 IS SET
AUX-ADC IS BUSY AUX-ADC DATA READY
MSB BIT D9 (DOUT)
LSB BIT D0 (DOUT)
LSB BIT D0 (HELD)
DOUT TRISTATED BIT AD0 CLEARED
Figure 6. Serial-Interface Timing Diagram ______________________________________________________________________________________ 25
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after either the 16-bit serial command is latched into the MAX19707 by a CS transition high (SPI controlled) or a T/R logic transition (external Tx-Rx control). In FAST mode, the recovery time is 0.5s to switch between Tx or Rx modes. the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant clock jitter limits the SNR performance of the on-chip Rx ADC as follows: 1 SNR = 20 x log 2 x x fIN x t AJ where fIN represents the analog input frequency and tAJ is the time of the clock jitter. Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX19707 clock input operates with an OVDD / 2 voltage threshold and accepts a 50% 15% duty cycle.
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of
CS
SCLK 16-BIT SERIAL DATA INPUT
DIN
D0-D9
ADC DIGITAL OUTPUT SINAD SETTLES WITHIN 1dB tWAKE, SD, ST_ TO Rx MODE OR tENABLE, RX DAC ANALOG OUTPUT OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ TO Tx MODE OR tENABLE, TX tENABLE, TX EXTERNAL T/R CONTROL
ID/QD
T/R Rx - > Tx tENABLE, RX EXTERNAL T/R CONTROL T/R Tx - > Rx
Figure 7. Mode-Recovery Timing Diagram
26
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
12-Bit Auxiliary Control DACs
The MAX19707 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1s settling time for controlling VGA, AGC, and AFC functions. The aux-DAC output range is 0.1V to 2.56V. During power-up, the VGA and AGC outputs (DAC2 and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V during power-up. The aux-DACs can be independently controlled through the SPI bus, except during SHDN mode where the aux-DACs are turned off completely and the output voltage is set to zero. In STBY and IDLE modes, the aux-DACs maintain the last value. On wakeup from SHDN, the aux-DACs resume the last values. Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200k. If capacitive loading exceeds 5pF, then add a 10k resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time. determines the internal reference of the auxiliary ADC (see Table 12). Bits AD2 and AD3 determine the auxiliary ADC input source (see Table 13). Bits AD4, AD5, and AD6 select the number of averages taken when a single start-convert command is given. The conversion time increases as the number of averages increases (see Table 14). The conversion clock can be divided down from the system clock by properly setting bits AD7, AD8, and AD9 (see Table 15). The aux-ADC output data can be written out of DOUT by setting bit AD10 high (see Table 16). The aux-ADC features a 4:1 input multiplexer to allow measurements on four input sources. The input sources are selected by AD3 and AD2 (see Table 13). Two of the multiplexer inputs (ADC1 and ADC2) can be connected to external sources such as an RF power detector like the MAX2208 or temperature sensor like the MAX6613. The other two multiplexer inputs are internal connections to VDD and OVDD that monitor the powersupply voltages. The internal VDD and OVDD connections are made through integrated resistor-dividers that yield VDD / 2 and OVDD / 2 measurement results. The aux-ADC voltage reference can be selected between an internal 2.048V bandgap reference or V DD (see Table 12). The VDD reference selection is provided to allow measurement of an external voltage source with a full-scale range extending beyond the 2.048V level. The input source voltage range cannot extend above VDD.
10-Bit, 333ksps Auxiliary ADC
The MAX19707 integrates a 10-bit, 333ksps aux-ADC with an input 4:1 multiplexer. In the aux-ADC mode register, setting bit AD0 begins a conversion with the auxiliary ADC. Bit AD0 automatically clears when the conversion is complete. Setting or clearing AD0 during a conversion has no effect (see Table 11). Bit AD1
Table 11. Auxiliary ADC Convert
AD0 0 1 SELECTION Aux-ADC Idle (Default) Aux-ADC Start-Convert
Table 13. Auxiliary ADC Input Source
AD3 0 0 1 1 AD2 0 1 0 1 AUX-ADC INPUT SOURCE ADC1 (Default) ADC2 VDD / 2 OVDD / 2
Table 12. Auxiliary ADC Reference
AD1 0 1 SELECTION Internal 2.048V Reference (Default) Internal VDD Reference
______________________________________________________________________________________
27
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK). An SPI-programmable divider divides the system clock by the appropriate divisor (set with bits AD7, AD8, and AD9; see Table 15) and provides the conversion clock to the auxiliary ADC. The auxiliary ADC has a maximum conversion rate of 333ksps. The maximum conversion clock frequency is 4MHz (333ksps x 12 clocks). Choose the proper divider value to keep the conversion clock frequency under 4MHz, based upon the system CLK frequency supplied to the MAX19707 (see Table 15). The total conversion time (tCONV) of the auxiliary ADC can be calculated as t CONV = (12 x N AVG x N DIV) / f CLK; where N AVG is the number of averages (see Table 14), NDIV is the CLK divisor (see Table 15), and fCLK is the system CLK frequency. DOUT is normally in a tri-state condition. Upon setting the auxiliary ADC start conversion bit (bit AD0), DOUT becomes active and goes high, indicating that the auxADC is busy. When the conversion cycle is complete (including averaging), the data is placed into an output register and DOUT goes low, indicating that the output data is ready to be driven onto DOUT. When bit AD10 is set (AD10 = 1), the aux-ADC enters a data output mode where data is available on DOUT upon the next assertion low of CS. The auxiliary ADC data is shifted out of DOUT (MSB first) with the data transitioning on the falling edge of the serial clock (SCLK). DOUT enters tristate condition when CS is deasserted high. When bit AD10 is cleared (AD10 = 0), the aux-ADC data is not available on DOUT (see Table 16). DIN can be written independent of DOUT state. A 16bit instruction at DIN updates the device configuration. To prevent modifying internal registers while reading data from DOUT, hold DIN at a high state. This effectively writes all ones into address 1111. Since address 1111 does not exist, no internal registers are affected.
MAX19707
Table 14. Auxiliary ADC Averaging
AD6 0 0 0 0 1 1 1 AD5 0 0 1 1 0 0 1 AD4 0 1 0 1 0 1 X AUX-ADC AVERAGING 1 Conversion (No Averaging) (Default) Average of 2 Conversions Average of 4 Conversions Average of 8 Conversions Average of 16 Conversions Average of 32 Conversions Average of 32 Conversions
X = Don't care.
Table 15. Auxiliary ADC Clock (CLK) Divider
AD9 0 0 0 0 1 1 1 1 AD8 0 0 1 1 0 0 1 1 AD7 0 1 0 1 0 1 0 1 AUX-ADC CONVERSION CLOCK CLK Divided by 1 (Default) CLK Divided by 2 CLK Divided by 4 CLK Divided by 8 CLK Divided by 16 CLK Divided by 32 CLK Divided by 64 CLK Divided by 128
Table 16. Auxiliary ADC Data Output Mode
AD10 0 1 SELECTION Aux-ADC Data is Not Available on DOUT (Default) Aux-ADC Enters Data Output Mode Where Data is Available on DOUT
28
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Table 17. Reference Modes
VREFIN > 0.8V x VDD REFERENCE MODE Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Buffered External Reference Mode. An external 1.024V 10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor.
1.024V 10%
Reference Configurations
The MAX19707 features an internal precision 1.024V bandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (V REFIN ) sets the reference operation mode (Table 17). In internal reference mode, connect REFIN to V DD. V REF is an internally generated 0.512V 4%. COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, V REFP = V DD / 2 + V REF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In buffered external reference mode, apply 1.024V 10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33F capacitor. Bypass REFIN to GND with a 0.1F capacitor. In this mode, the Tx DAC full-scale output is proportional to the external reference. For example, if the VREFIN is increased by 10% (max), the Tx DAC fullscale output is also increased by 10% or 440mV.
25 IAP 0.1F VIN COM 0.33F 0.1F 22pF
IAN 25 22pF
MAX19707
25 QAP 0.1F VIN 22pF
0.33F
0.1F
QAN 25 22pF
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX19707 provides better SFDR and THD with fully differential input signals than single-ended signals,
Figure 8. Balun Transformer-Coupled Single-Ended-toDifferential Input Drive for Rx ADC
especially for high input frequencies. In differential mode, even-order harmonics are lower as both inputs (IAP, IAN, QAP, QAN) are balanced, and each of the Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 9 shows an RF transformer converting the MAX19707 Tx DAC differential analog outputs to single-ended.
______________________________________________________________________________________
29
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Using Op-Amp Coupling
IDP VOUT
MAX19707
IDN
QDP
VOUT
QDN
Figure 9. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC
Drive the MAX19707 Rx ADC with op amps when a balun transformer is not available. Figures 10 and 11 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications. Amplifiers such as the MAX4454 and MAX4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. The op-amp circuit shown in Figure 11 can also be used to interface with the Tx DAC differential analog outputs to provide gain or buffering. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode level. Also, the Tx DAC analog outputs are designed to drive a differential input stage with input impedance 70k. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conversion and select an amplifier with proper input commonmode voltage range.
TDD Mode
REFP
VIN
1k 0.1F
RISO 50 IAP CIN 22pF
100
1k
COM REFN 0.1F RISO 50 100 IAN CIN 22pF REFP
The MAX19707 is optimized to operate in TDD applications. When FAST mode is selected, the MAX19707 can switch between Tx and Rx modes through the T/R pin in typically 0.5s. The Rx ADC and Tx DAC operate independently. The Rx ADC and Tx DAC digital bus are shared forming a single 10-bit parallel bus. Using the 3wire serial interface or external T/R pin, select between Rx mode to enable the Rx ADC or Tx mode to enable the Tx DAC. When operating in Rx mode, the Tx DAC bus is not enabled and in Tx mode the Rx ADC bus is tri-stated, eliminating any unwanted spurious emissions and preventing bus contention. In TDD mode, the MAX19707 uses 84.6mW power at fCLK = 45MHz.
TDD Application
MAX19707
VIN
0.1F
1k
RISO 50 QAP CIN 22pF
100
1k
Figure 12 illustrates a typical TDD application circuit. The MAX19707 interfaces directly with the radio frontends to provide a complete "RF-to-Bits" solution for TDD applications such as 802.11, 802.16, DSRC, and proprietary radio systems. The MAX19707 provides several system benefits to digital baseband developers. * Fast Time-to-Market * High-Performance, Low-Power Analog Functions Low Risk, Proven Analog Front-End Solution No Mixed-Signal Test Times No NRE Charges No IP Royalty Charges Enables Digital Baseband to Scale with 65nm to 90nm CMOS *
REFN
0.1F RISO 50
*
QAN
100
* * *
CIN 22pF
Figure 10. Single-Ended Drive for Rx ADC
30
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
R4 600 R5 600
R1 600
RISO 22 IAN CIN 5pF
R2 600 R6 600 R3 600 R8 600 R7 600 R9 600 COM
MAX19707
RISO 22 CIN 5pF IAP
R10 600
R11 600
Figure 11. Rx ADC DC-Coupled Differential Drive
10-BIT ADC Rx-I 802.11X Rx-Q ZIF TRANSCEIVER 10-BIT DAC Tx-I Tx SOURCE CLK DIGITAL BASEBAND ASIC SYSTEM CONTROL CLK DIST SPI REG SCLK DIN CS SHDN HALFDUPLEX BUS D9 D0 Rx ENCODE T/R
AGC
Tx-Q 12-BIT DAC DAC3 DAC2
TCXO
DAC1
MAX19707
VDD 0VDD BATTERY VOLTAGE MONITOR TEMPERATURE MEASURE 4:1 MUX ADC 10-BIT, 333ksps
REF 1.024V BUFFER
REFIN REFP REFN COM DOUT
Figure 12. Typical Application Circuit for 802.11 Radio ______________________________________________________________________________________ 31
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Grounding, Bypassing, and Board Layout
The MAX19707 requires high-speed board layout design techniques. Refer to the MAX19707 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass OVDD to OGND with a 0.1F ceramic capacitor in parallel with a 2.2F capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33F ceramic capacitor. Bypass REFIN to GND with a 0.1F capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital outputdriver ground (OGND) on the device package. Connect the MAX19707 exposed backside paddle to GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. Make this connection with a low-value, surfacemount resistor (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system's ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the device are measured using the best-straight-line fit (DAC Figure 13a). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 13b). ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 13a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming.
7 6 ANALOG OUTPUT VALUE 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (0.25 LSB) AT STEP 011 (0.5 LSB) ANALOG OUTPUT VALUE
6 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+0.25 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-0.25 LSB)
Figure 13a. Integral Nonlinearity 32
Figure 13b. Differential Nonlinearity
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10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: (V22 + V32 + V42 + V52 + V62 THD = 20 x log V1 )
MAX19707
ADC Dynamic Parameter Definitions
Aperture Jitter Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC's resolution (N bits): SNR(max) = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
where V1 is the fundamental amplitude and V2-V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 f2), (2 f1), (2 f2), (2 f1 f2), (2 f2 f1). The individual input tone levels are at -7dBFS. 3rd-Order Intermodulation (IM3) IM3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The 3rd-order intermodulation products are (2 x f1 f2), (2 f2 f1). The individual input tone levels are at -7dBFS.
CLK
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 14. T/H Aperture Timing
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33
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed 5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in so that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental: (V22 + V32 + ...+ Vn2 ) THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC.
Selector Guide
PART MAX19700 DESCRIPTION Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA Filters, Three 12-Bit Auxiliary DACs Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA Filters, Three 12-Bit Auxiliary DACs, 10-Bit Auxiliary ADC with 4:1 Input Mux Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Three 12-Bit Auxiliary DACs, 10-Bit Auxiliary ADC with 4:1 Input Mux SAMPLING RATE (Msps) 7.5
MAX19708
11
MAX19705/MAX19706/MAX19707
7.5/22/45
34
______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Functional Diagram
VDD = 2.7V TO 3.3V OVDD = 1.8V TO 3.3V
IAP IAN
10-BIT ADC
MAX19707
SHDN T/R
QAP QAN
10-BIT ADC HALFDUPLEX BUS 10-BIT DAC
D0-D9
IDP IDN
QDP QDN
10-BIT DAC
SYSTEM CLOCK
CLK
PROGRAMMABLE OFFSET/CM DAC1 12-BIT DAC
SERIAL INTERFACE AND SYSTEM CONTROL
DIN SCLK CS
DAC2
12-BIT DAC
1.024V REFERENCE BUFFER
REFIN REFP REFN COM
DAC3 VDD 0VDD ADC1 ADC2 4:1 MUX
12-BIT DAC
10-BIT ADC
DOUT
GND
OGND
______________________________________________________________________________________
35
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 k
C L
E2
C L
C L
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
1
2
36
______________________________________________________________________________________
32, 44, 48L QFN.EPS
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX19707
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
2
2
Revision History
Pages changed at Rev 1: 1, 4, 6, 7, 10-15, 17, 33, 35, 36, 37
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37 (c) 2007 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.

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